| CompOrg Spring 2004 Lab |
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The code needed for this lab is in ~hollingd/public/lab9 on monte.cs.rpi.edu, there is also a tar file available: lab9.tar. You will need a complete copy of these files to work on this lab:
> cp -r ~hollingd/public/lab9 . > cd lab9
There are a number of files that are needed to build a Y86 simulator given an file that contains a description of the control system specified in HCL. There are currently two HCL files:
seq-std.hcl: contains HCL for standard Y86 sequential implementation. seq-inc.hcl: includes support for increment "incl" instruction.
There is a Makefile already constructed for your use with this lab. You can build the 'standard' simulator by typing "make ssim" when in the directory holding the files (your copy of the directory). This simulator can only handle the standard Y86 instructions. You can run the Y86 code you developed in lab8 using this simulator.
The Makefile will also build a simulator that includes an incl instruction, this simulator is based on the hcl file seq-inc.hcl. The README file contains a description of what was added to the standard hcl file to implement the new instruction.
NOTE: There is also a colorized version of this file (with changes shown in red) available : seq-inc.hcl.html
You should build and test both simulators. Recall that to assemble a Y86 program you use the "yas" program, you need to use the version of "yas" that is included with the lab9 files. The asum.ys program from last lab can be tested with "ssim", and there is also a new version of this program (named asum-inc.ys) that uses the "incl" instruction - you can test this with the "sinc" simulator:
> ./yas asum.ys > ./ssim asum.yo ... IF: Fetched addl at 0x65. ra=%ebx, rb=%ecx, valC = 0x0 IF: Fetched irmovl at 0x67. ra=----, rb=%ebx, valC = 0xffffffff IF: Fetched addl at 0x6d. ra=%ebx, rb=%edx, valC = 0x0 IF: Fetched jne at 0x6f. ra=----, rb=----, valC = 0x57 IF: Fetched popl at 0x74. ra=%ebp, rb=----, valC = 0x0 IF: Fetched ret at 0x76. ra=----, rb=----, valC = 0x0 IF: Fetched halt at 0x39. ra=----, rb=----, valC = 0x0 46 instructions executed Exception status = HLT Condition Codes: Z=1 S=0 O=0 Changed Register State: %eax: 0x00000000 0x0000abcd %ecx: 0x00000000 0x00000024 %ebx: 0x00000000 0xffffffff %esp: 0x00000000 0x000000f8 %ebp: 0x00000000 0x00000100 %esi: 0x00000000 0x0000a000 Changed Memory State: 0x00f0: 0x00000000 0x00000100 0x00f4: 0x00000000 0x00000039 0x00f8: 0x00000000 0x00000014 0x00fc: 0x00000000 0x00000004 > ./yas asum-inc.ys ... IF: Fetched incl at 0x65. ra=%ecx, rb=----, valC = 0x0 IF: Fetched irmovl at 0x67. ra=----, rb=%ebx, valC = 0xffffffff IF: Fetched addl at 0x6d. ra=%ebx, rb=%edx, valC = 0x0 IF: Fetched jne at 0x6f. ra=----, rb=----, valC = 0x57 IF: Fetched popl at 0x74. ra=%ebp, rb=----, valC = 0x0 IF: Fetched ret at 0x76. ra=----, rb=----, valC = 0x0 IF: Fetched halt at 0x39. ra=----, rb=----, valC = 0x0 54 instructions executed Exception status = HLT Condition Codes: Z=1 S=0 O=0 Changed Register State: %eax: 0x00000000 0x0000abcd %ecx: 0x00000000 0x00000024 %ebx: 0x00000000 0xffffffff %esp: 0x00000000 0x000000f8 %ebp: 0x00000000 0x00000100 %esi: 0x00000000 0x0000a000 Changed Memory State: 0x00f0: 0x00000000 0x00000100 0x00f4: 0x00000000 0x00000039 0x00f8: 0x00000000 0x00000014 0x00fc: 0x00000000 0x00000004
Note: You can run the program asum.yo using the new simulator, it should work fine (the new simulator just adds the capability of handling the incl instruction). You can't run the new asum-inc.yo program using the old simulator (ssim) since it doesn't know what to make of the incl instruction.
Your job in this lab is to create a new Y86 simulator that supports an instruction named "dbl":
dbl rA,rB
This instruction should set rB to be twice the value in rA (double the value of the first register and store the result in the second register).
Your first step is to determine what needs to happen during each stage in the processing of the instruction. Dave will have some copies of fig 4.21 samples and empty tables printed out to help with this...
Once you know what needs to happen for the dbl instruction to work, you need to create a file that contains the HCL that includes any changes to support the new instruction. You should start by copying the standard hcl file:
cp seq-std.hcl seq-dbl.hcl
Once you have made all the changes you think are necessary, you can try to build s simulator by typing "make sdbl" (there are rules in the Makefile to build this for you - make sure your hcl file is named "seq-dbl.hcl"). You should see something like this:
> make sdbl # Building the seq-dbl.hcl version of SEQ ./hcl2c -n seq-dbl.hclseq-dbl.c gcc -Wall -O2 -o sdbl \ seq-dbl.c ssim.c isa.c -lm
Write some test code (a Y86 program) that uses the dbl instruction and test your simulator. Once you think your simulator has a correct implementation of the double instruction, assemble and run the program named tdbl.ys:
> ./yas tdbl.ys > ./sdbl tdbl.yo ... IF: Fetched dbl at 0x31. ra=%eax, rb=%ebx, valC = 0x0 IF: Fetched rrmovl at 0x33. ra=%ebx, rb=%eax, valC = 0x0 IF: Fetched irmovl at 0x35. ra=----, rb=%edx, valC = 0xffffffff IF: Fetched addl at 0x3b. ra=%edx, rb=%ecx, valC = 0x0 IF: Fetched jmp at 0x3d. ra=----, rb=----, valC = 0x2a IF: Fetched andl at 0x2a. ra=%ecx, rb=%ecx, valC = 0x0 IF: Fetched je at 0x2c. ra=----, rb=----, valC = 0x42 IF: Fetched popl at 0x42. ra=%ebp, rb=----, valC = 0x0 IF: Fetched ret at 0x44. ra=----, rb=----, valC = 0x0 IF: Fetched halt at 0x19. ra=----, rb=----, valC = 0x0 70 instructions executed Exception status = HLT Condition Codes: Z=1 S=0 O=0 Changed Register State: %eax: 0x00000000 0x00000100 %edx: 0x00000000 0xffffffff %ebx: 0x00000000 0x00000100 %esp: 0x00000000 0x000000fc %ebp: 0x00000000 0x00000100 Changed Memory State: 0x00f4: 0x00000000 0x00000100 0x00f8: 0x00000000 0x00000019 0x00fc: 0x00000000 0x00000008