Test #2 will be given in class on Friday, April 9th. The test is closed book, no notes or computers are allowed.

An IA32 Instruction reference will be distributed with the test.

A copy of figure 4.21 will also be provided during the test, as well as a description of the Y86 instruction set and an HCL reference will also be provided.

Topic	What to know	What to expect on the test
IA32 Assembly Language	IA32 Assembly language (IA32 Instruction Set). Subroutines (gcc/gas calling conventions).	Be able to write IA32 Assembly language programs and subroutines (subroutines that will work with code generated by gcc). You may be given a description of what the code should do in English, or as a C program/function. Given some IA32 Assembly language code, provide C code that does the same thing. Know the stack! Be able to answer questions about how subroutines use the stack (and buffer overflow).
Processor Architecture - Sequential	Y86 Instruction Set Simple Combinational Circuits HCL Memory and Clocking Stages of Y86 Instructions: Fetch Decode Execute Memory Write Back PC Update HCL for Y86 Sequential Implementation	Be able to rewrite some IA32 code segments using only the Y86 instruction set Be able to describe some simple combinational circuits using HCL. Be able to describe the operation of simple memory elements (registers), specifically how a value is read from a register and how a new value is stored in a register (what signals are necessary, when do things happen, etc.) Be able to describe what happens during each of the 6 stages for any Y86 Instruction, including new instructions (same idea as the homework assignment). Given Figure 4.21 and a list of controls, derive the HCL expressions the describe each control to support various some set of instructions (or modify a given set of HCL expressions).
Pipelining and a Y86 Pipeline	Pipelining and it's impact on performance. Pipeline registers Data Hazards Control Hazards Y86 Pipeline conditional branching issues why is RET special?	Given a description of a sequential implementation of an instruction set, and a pipelined version, be able to discuss the potential performance improvements. Be able to discuss data and control hazards (general issues). Be able to identify data and control hazards in a sequence of Y86 instructions (assuming the pipeline described in the Text). Be able to discuss ways to (attempt to) avoid stalling the pipeline given a a sequence of Y86 instructions.

Practice Problems

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• Practice Problem 3.3 (know leal!)

• Practice Problem 3.24 (Buffer Overflow)

• Problem 3.31 (Assembly to C)

• Problem 3.36 (Assembly to C)

• Practice problem 4.3 (Y86 Instruction Set)

• Practice Problem 4.8 (HCL)

• Practice Problems 4.9,4.10,4.11,4.12,4.13 (Y86 Instructions)

• Practice Problem 4.14,4.15,4.16,4.18 (HCL)

• Practice Problem 4.21 (Pipelining)

• Practice Problem 4.22 (Pipeline Performance)

• Identify the hazards in the following code, and show any stall cycles that need to be inserted in order to avoid all the hazards

        irmovl $100,%edx
        addl %edx,%eax
        rmmovl %eax,-12(%ebp)
        addl %eax,%eax
        jle  foo
        rrmovl %edx,%eax
  foo: