| CompOrg Fall 2005 Lab |
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The code needed for this lab is in ~hollingd/public/lab11, there is also a tar file available: lab11.tar. You will need a complete copy of these files to work on this lab:
> cp -r ~hollingd/public/lab11 . > cd lab11
There are a number of files that are needed to build a Y86 simulator given an file that contains a description of the control system specified in HCL. There are currently two HCL files:
seq-std.hcl: contains HCL for standard Y86 sequential implementation. seq-inc.hcl: includes support for increment "incl" instruction.
There is a Makefile already constructed for your use with this lab. You can build the 'standard' simulator by typing "make ssim" when in the directory holding the files (your copy of the directory). This simulator can only handle the standard Y86 instructions. You can run the Y86 code you developed in lab9 using this simulator.
The Makefile will also build a simulator that includes an incl instruction, this simulator is based on the hcl file seq-inc.hcl. The README file contains a description of what was added to the standard hcl file to implement the new instruction.
NOTE: There is also a colorized version of this file (with changes shown in red) available : seq-inc.hcl.html
You should build and test both simulators. Recall that to assemble a Y86 program you use the "yas" program, you need to use the version of "yas" that is included with the lab11 files The asum.ys program from last lab can be tested with "ssim", and there is also a new version of this program (named asum-inc.ys) that uses the "incl" instruction - you can test this with the "sinc" simulator:
> ./yas asum.ys > ./sim/ssim asum.yo ... IF: Fetched addl at 0x65. ra=%ebx, rb=%ecx, valC = 0x0 IF: Fetched irmovl at 0x67. ra=----, rb=%ebx, valC = 0xffffffff IF: Fetched addl at 0x6d. ra=%ebx, rb=%edx, valC = 0x0 IF: Fetched jne at 0x6f. ra=----, rb=----, valC = 0x57 IF: Fetched popl at 0x74. ra=%ebp, rb=----, valC = 0x0 IF: Fetched ret at 0x76. ra=----, rb=----, valC = 0x0 IF: Fetched halt at 0x39. ra=----, rb=----, valC = 0x0 46 instructions executed Exception status = HLT Condition Codes: Z=1 S=0 O=0 Changed Register State: %eax: 0x00000000 0x0000abcd %ecx: 0x00000000 0x00000024 %ebx: 0x00000000 0xffffffff %esp: 0x00000000 0x000000f8 %ebp: 0x00000000 0x00000100 %esi: 0x00000000 0x0000a000 Changed Memory State: 0x00f0: 0x00000000 0x00000100 0x00f4: 0x00000000 0x00000039 0x00f8: 0x00000000 0x00000014 0x00fc: 0x00000000 0x00000004 > ./yas asum-inc.ys > ./sim/sinc asum-inc.yo ... IF: Fetched incl at 0x65. ra=%ecx, rb=----, valC = 0x0 IF: Fetched irmovl at 0x67. ra=----, rb=%ebx, valC = 0xffffffff IF: Fetched addl at 0x6d. ra=%ebx, rb=%edx, valC = 0x0 IF: Fetched jne at 0x6f. ra=----, rb=----, valC = 0x57 IF: Fetched popl at 0x74. ra=%ebp, rb=----, valC = 0x0 IF: Fetched ret at 0x76. ra=----, rb=----, valC = 0x0 IF: Fetched halt at 0x39. ra=----, rb=----, valC = 0x0 54 instructions executed Exception status = HLT Condition Codes: Z=1 S=0 O=0 Changed Register State: %eax: 0x00000000 0x0000abcd %ecx: 0x00000000 0x00000024 %ebx: 0x00000000 0xffffffff %esp: 0x00000000 0x000000f8 %ebp: 0x00000000 0x00000100 %esi: 0x00000000 0x0000a000 Changed Memory State: 0x00f0: 0x00000000 0x00000100 0x00f4: 0x00000000 0x00000039 0x00f8: 0x00000000 0x00000014 0x00fc: 0x00000000 0x00000004
Note: You can run the program asum.yo using the new simulator, it should work fine (the new simulator just adds the capability of handling the incl instruction). You can't run the new asum-inc.yo program using the old simulator (ssim) since it doesn't know what to make of the incl instruction.
Your job in this lab is to build a new Y86 simulator that supports the instructions "dbl" and "leave" you worked on last week. NOTE: The dbl instruction we worked on last week is not exactly the same as what you are working on today - the register has changed from rB to rA. Start by getting "dbl" to work (this is the easy one), then add support for the "leave" instruction.
dbl rA
This instruction should set rA to be twice the value in rA (double the value of the register and store the result in the same register).
Your first step is to determine what needs to happen during each stage in the processing of the instructions, you did this last week. For similar instructions.
Once you know what needs to happen for the dbl and leave instructions to work, you need to create a file that contains the HCL that includes any changes to support the new instruction. You should "cd" to the sim directory of your copy of the lab11 files, and then make a copy of the standard hcl file:
cp seq-std.hcl seq-dbl.hcl
Once you have made all the changes you think are necessary, you can try to build a simulator (by typing "make sdbl" (there are rules in the Makefile to build this for you - make sure your hcl file is named "seq-dbl.hcl"). You should see something like this:
> make sdbl # Building the seq-dbl.hcl version of SEQ ./hcl2c -n seq-dbl.hclseq-dbl.c gcc -Wall -O2 -o sdbl \ seq-dbl.c ssim.c isa.c -lm
There is some test code (a Y86 program) that you can use to make
sure your double instruction is working in the testcode directory
of the lab11 files. The program is pow.ys,
it uses the dbl instruction to compute powers of two.
Once you think your simulator has a correct
implementation of the double instruction, assemble and run the program:
> ./yas pow.ys > ./sim/sdbl pow.yo IF: Fetched jne at 0x40. ra=----, rb=----, valC = 0x36 IF: Fetched dbl at 0x36. ra=%eax, rb=----, valC = 0x0 IF: Fetched irmovl at 0x38. ra=----, rb=%ecx, valC = 0xffffffff IF: Fetched addl at 0x3e. ra=%ecx, rb=%edx, valC = 0x0 IF: Fetched jne at 0x40. ra=----, rb=----, valC = 0x36 IF: Fetched dbl at 0x36. ra=%eax, rb=----, valC = 0x0 IF: Fetched irmovl at 0x38. ra=----, rb=%ecx, valC = 0xffffffff IF: Fetched addl at 0x3e. ra=%ecx, rb=%edx, valC = 0x0 IF: Fetched jne at 0x40. ra=----, rb=----, valC = 0x36 IF: Fetched popl at 0x45. ra=%ebp, rb=----, valC = 0x0 IF: Fetched ret at 0x47. ra=----, rb=----, valC = 0x0 IF: Fetched halt at 0x1e. ra=----, rb=----, valC = 0x0 31 instructions executed Exception status = HLT Condition Codes: Z=1 S=0 O=0 Changed Register State: %eax: 0x00000000 0x00000010 %ecx: 0x00000000 0xffffffff %esp: 0x00000000 0x000000fc %ebp: 0x00000000 0x00000100 Changed Memory State: 0x00f4: 0x00000000 0x00000100 0x00f8: 0x00000000 0x0000001e 0x00fc: 0x00000000 0x00000004
Once "dbl" is working, add the leave instruction in the same way. The Makefile in the sim directory will build a simulator named "sleave" from the hcl file "seq-leave.hcl" for you (type "make sleave"). The testcode asum_r.ys is a recursive version of the asum.ys program (uses recursion to sum the elements of an array - this gives your leave instruction a workout). Make sure your new simulator can handle this program, a program that calls leave only once does not throughly test it!
> cd sim > cp seq-std.hcl seq-leave.hcl > emacs seq-leave.hcl... > make sleave ./hcl2c -n seq-leave.hclseq-leave.c gcc -Wall -O2 -o sleave \ seq-leave.c ssim.c isa.c -lm > cd .. > ./yas testcode/asum_r.ys > sim/sleave testcode/asum_r.yo ... IF: Fetched leave at 0x86. ra=----, rb=----, valC = 0x0 IF: Fetched ret at 0x87. ra=----, rb=----, valC = 0x0 IF: Fetched popl at 0x72. ra=%ebx, rb=----, valC = 0x0 IF: Fetched popl at 0x74. ra=%ebx, rb=----, valC = 0x0 IF: Fetched mrmovl at 0x76. ra=%ecx, rb=%ebp, valC = 0x8 IF: Fetched mrmovl at 0x7c. ra=%ebx, rb=%ecx, valC = 0x0 IF: Fetched addl at 0x82. ra=%ebx, rb=%eax, valC = 0x0 IF: Fetched popl at 0x84. ra=%ebx, rb=----, valC = 0x0 IF: Fetched leave at 0x86. ra=----, rb=----, valC = 0x0 IF: Fetched ret at 0x87. ra=----, rb=----, valC = 0x0 IF: Fetched halt at 0x39. ra=----, rb=----, valC = 0x0 112 instructions executed Exception status = HLT Condition Codes: Z=0 S=0 O=0 Changed Register State: %eax: 0x00000000 0x0000abcd %ecx: 0x00000000 0x00000014 %esp: 0x00000000 0x000000f8 %ebp: 0x00000000 0x00000100 Changed Memory State: 0x009c: 0x00000000 0x00000024 0x00a0: 0x00000000 0x000000b4 0x00a4: 0x00000000 0x00000072 0x00a8: 0x00000000 0x00000024 ...