CompOrg Fall 2003 - Homework #5

Y86 Sequential Implementation

Due Date: 11/20/03 (in class) Hardcopy only (no electronic submissions)

Late Penalty: 10% per day (7 day max)

We want to add some new instructions to the Y86 instruction set. Your job is to provide a description of what happens during each phase of each of the new instructions, and to modify the HCL expressions used to define the sequential implementation of the Y86 processor we have discussed in class.

The new instructions you need to add:

iaddl: adds a 32 bit value to a register
isubl: subtracts a 32 bit value from a register
iandl: bitwise AND of a 32 bit value and a register
ixorl: bitwise exclusive OR of a 32 bit value and a register
leave: prepares the stack when returning from a subroutine. This sets %esp to the value currently in %ebp, and then pops %ebp from the stack. This is functionally equivalent to the sequence of instructions:
```
rrmovl %ebp,%esp
popl   %ebp
```

Note that the first four can be treated as a new OP instruction named IOP (immediate OP), and implemented just like the OP instruction (one icode, different ifun values passed through to the ALU).

Here is a description of the machine code format for these new instructions (similar to the diagram on page 259 of the text):

You must use figure 4.21 as a description of the datapath (this is the same set of interconnections used by the other Y86 instructions we looked at).

For each of the new instructions you need to describe what needs to happen during each of the 6 stages. For each new instruction you should create a table similar to what we looked at in class (also figures 4.16, 4.17, 4.18 and 4.19) that describe the standard Y86 instructions. You can treat the 4 Immediate OP instructions as a single instruction (so you only need to describe 2 instructions: IOP and LEAVE).

You also must provide a set of modified HCL expressions that describe a sequential implementation of the standard y86 instructions as well as our new instructions. Below is a complete set of these expressions to use as a starting point (these don't cover the new instructions). Feel free to add whatever symbols you want (for example you probably want to use IIOP and ILEAVE to refer to the icode values C and D respectively.) Refer to Appendix A in the text for a description of HCL.


####################################################################
#    Control Signal Definitions.                                   #
####################################################################

################ Fetch Stage     ###################################

# Does fetched instruction require a regid byte?
bool need_regids =
	icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, 
		     IIRMOVL, IRMMOVL, IMRMOVL };

# Does fetched instruction require a constant word?
bool need_valC =
	icode in { IIRMOVL, IRMMOVL, IMRMOVL, IJXX, ICALL };

bool instr_valid = icode in 
	{ INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL,
	       IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL };

################ Decode Stage    ###################################

## What register should be used as the A source?
int srcA = [
	icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL  } : rA;
	icode in { IPOPL, IRET } : RESP;
	1 : RNONE; # Don't need register
];

## What register should be used as the B source?
int srcB = [
	icode in { IOPL, IRMMOVL, IMRMOVL  } : rB;
	icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP;
	1 : RNONE;  # Don't need register
];

## What register should be used as the E destination?
int dstE = [
	icode in { IRRMOVL, IIRMOVL, IOPL} : rB;
	icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP;
	1 : RNONE;  # Don't need register
];

## What register should be used as the M destination?
int dstM = [
	icode in { IMRMOVL, IPOPL } : rA;
	1 : RNONE;  # Don't need register
];

################ Execute Stage   ###################################

## Select input A to ALU
int aluA = [
	icode in { IRRMOVL, IOPL } : valA;
	icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valC;
	icode in { ICALL, IPUSHL } : -4;
	icode in { IRET, IPOPL } : 4;
	# Other instructions don't need ALU
];

## Select input B to ALU
int aluB = [
	icode in { IRMMOVL, IMRMOVL, IOPL, ICALL, 
		      IPUSHL, IRET, IPOPL } : valB;
	icode in { IRRMOVL, IIRMOVL } : 0;
	# Other instructions don't need ALU
];

## Set the ALU function
int alufun = [
	icode == IOPL : ifun;
	1 : ALUADD;
];

## Should the condition codes be updated?
bool set_cc = icode in { IOPL };

################ Memory Stage    ###################################

## Set read control signal
bool mem_read = icode in { IMRMOVL, IPOPL, IRET };

## Set write control signal
bool mem_write = icode in { IRMMOVL, IPUSHL, ICALL };

## Select memory address
int mem_addr = [
	icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : valE;
	icode in { IPOPL, IRET } : valA;
	# Other instructions don't need address
];

## Select memory input data
int mem_data = [
	# Value from register
	icode in { IRMMOVL, IPUSHL } : valA;
	# Return PC
	icode == ICALL : valP;
	# Default: Don't write anything
];

################ Program Counter Update ############################

## What address should instruction be fetched at

int new_pc = [
	# Call.  Use instruction constant
	icode == ICALL : valC;
	# Taken branch.  Use instruction constant
	icode == IJXX && Bch : valC;
	# Completion of RET instruction.  Use value from stack
	icode == IRET : valM;
	# Default: Use incremented PC
	1 : valP;
];

How to submit

Submission is via hardcopy only. Submissions are due by the end of class on Nov 20th (or will be considered late).

Grading

The descriptions of the new instructions must be in the format requested (tables similar to figs 4.16,17,18,19). Each of these is worth 25% of the grade.

Your modified HCL expressions are worth a total of 50% of the hw grade.