OpSys Spring 2005 - HW4 FAQ

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+ Generator code

Question:

You mentioned some generator code, is anything available? How does it work?


Answer:

There is a generator available: generate.pl. This is a perl program that generates input that can be used to test your simulator. The program includes many parameters (all variables set at the top of the program), so you can modify how it works. To run the program, save it as "generator.pl" and run "perl generator.pl" from the Unix command line.

The generator uses random numbers based on gaussian probability distribution (a bell curve) so that it generates addresses that are near each other. The program allows you to set the maximum number of concurrent simulated processes, total number of memory accesses, the size of virtual memory, number of accesses per quantum (as an average and standard deviation), etc.

This code is available for your use, but no claims are made about whether it is the best (or even a particularly good) representation of the memory access patterns of real processes. The generator is a minimal improvement over one based on generating addresses according to a uniform distribution (which is certainly not representative of what is observed in real programs).

Dave will go over this generator in class... (the ideas behind it, not the implementation).

+ Generator bug?

Question:

The sample generator seems to have a problem, it starts the same process twice without terminating it (I see two "S i" lines without any "T i" line in between).


Answer:

I cannot reproduce this error, and looking over the code I don't see how it is happening. Please tell me what parameter values you are using (send email to opsys@cs.rpi.edu).

+ Test Files and sample output

Question:

Can we have some test files?


Answer:

I've created some test files along with a description of what each input file does (each is targeted at checking a single algorithm for correctness). Everything is here - please look at the README file for a complete description and result of sample runs with my simulator.

NOTE: For the file "clock_testfile", the assumption is that only memory accesses count toward defining an "timestep", otherwise results will be different than I got...