Register hits		39 hits (32r + 7w)
Register misses		27 misses (5r + 22w, 40.9%)
Register writebacks	15 (55.6% of all misses)
Register reads		148 bytes
Register writes		116 bytes

L1 cache hits		28 hits (13r + 15w)
L1 cache misses		14 misses (14r + 0w, 33.3%)
L1 cache writebacks	0 (0% of all misses)
L1 cache reads		108 bytes
L1 cache writes		60 bytes

Main memory reads	448 bytes
Main memory writes	0 bytes

Total clock cycles	490 clocks
Total			28 hits, 14 misses, 490 cycles
Iterator type		23 hits, 12 misses, 419 cycles
Value type		4 hits, 1 misses, 37 cycles
Difference type		1 hits, 1 misses, 34 cycles
Pointer type		0 hits, 0 misses, 0 cycles