Computer Science 2500 Computer Organization Rensselaer Polytechnic Institute Spring 2009

For the final lab assignment, you are to implement a simulator for the pipelined datapath and control for our MIPS subset as described in Chapter 4 of the 4th Edition of Patterson and Hennessy.

You may work alone, but you are encouraged to work in a group of 2 or 3. Those intending to work in a group must notify me via email by Friday, April 17.

Requirements

The main loop of your program should be similar to that of your single-cycle simulator from the previous lab. Your completed lab 7 would make a good starting point for your implementation of this lab. We will once again make the simplifying assumption that we can access both instruction and data memory simultaneously, and that both will store/retrieve values from a common memory.

You should be able to process the same user commands, plus a new command pipeline that will print the values in your pipeline registers. Note that the run command should run for the specified number of clock cycles rather than the specified number of instructions.

Your program should the pipelined system as described through Section 4.8. This includes:

1. The basic pipeline datapath and control as shown in Figure 4.51.
2. A forwarding system to limit the need for pipeline stalls, as described in Section 4.7.
3. A hazard detection system to insert a bubble into the pipeline when a lw instruction writes to a register that is needed by the next instruction (as in Figure 4.58).
4. The early computation and detection of branches to limit the need for stalls following branch or jump instructions, and the ability to insert a bubble when necessary, as shown in Figure 4.62.

At the start of the simulation, only the first stage of the pipeline will be doing useful work. You will need to take care to ensure that subsequent stages do not perform any meaningful computations (i.e., those which have any effect on the PC, registers, or memory).

When the simulation ends (by loading the special value 0xffffffff as the next instruction), you will need to "drain" the pipeline to complete the partially-executed instructions before stopping.

Submission and Grading

When you are finished, you are to submit your source code (please include all C source and header files and your Makefile, but no object files or executables) using the submit utility as lab8.

Your program will be graded on how accurately it simulates the pipelined cycle implementation and on the documentation of your simulator. A "working" simulator that executes the MIPS instructions without properly simulating the underlying pipelined datapath and control will be eligible for very little credit. A program that implements the basic pipeline but which lacks forwarding and/or hazard detection will still be eligible for signficant credit.

In addition to the example programs provided, you should develop a few of your own programs to make sure you test all required functionality. Please include your tests in your submission. We will use my own tests, your submitted tests, plus the ones provided, to aid in grading. Each individual working on the submission must contribute two MIPS programs for testing.