Course Schedule

"P&H" indicates readings from Patterson and Hennessy. Additional

readings will be given occasionally. Links will be added here with additional information about lectures, labs, and other assignments. All assignment dates are subject to change, and are provided only as a general guideline until the actual assignment is handed out in class.

Date Topic and/or Event Readings
Jan. 13 Introduction and Overview; Bits and Numbers P&H Ch. 1, Ch. 2.4, Topic notes: Introduction and Overview; Bits and Numbers, Topic notes: Bits and Bytes and Numbers
Jan. 16 Bitwise Operations; Floating Point Representations; C and Unix; Lab 1: Bit Manipulations in C P&H Ch. 3, Topic notes: C and Unix
Jan. 20 More C and Unix
Jan. 23 More C and Unix; Instruction Set Architecture; MIPS Assembly: Simple Arithmetic, Registers P&H Ch. 2.1-2.3, Topic Notes: MIPS ISA
Jan. 27 MIPS ISA: Instruction Formats, Logical Operations, Branches; Lab 2: Decoding MIPS Instructons P&H Ch. 2.5-2.7
Jan. 30 No Class - Instructor Out of Town
Feb. 3 MIPS Programming Topic Notes: MIPS Programming
Feb. 6 MIPS Programming; Lab 3: MIPS Programming in SPIM
Feb. 10 Introduction to Digital Logic; Lab 4: MIPS Insertion Sort Topic Notes: Digital Logic, P&H App. C.1-C.2 (on the CD)
Feb. 13 Digital Logic; Combinational Circuits P&H App. C.3
Feb. 17 No Class - RPI on Monday Schedule -
Feb. 20 More Combinational Circuits: Arithmetic Logic Units P&H App. C.5-C.6
Feb. 24 Sequential Circuits: Clocks, Latches, Flip-Flops, Counters; Lab 5: Sequential Circuits Topic Notes: Sequential Circuits; P&H App. C.7-C.8
Feb. 27 Exam Review; Building Memory Topic Notes: Building Memory; P&H App. C.9
Mar. 3 Exam 1 (everything up to MIPS Programming)
Mar. 6 No Class - Instructor on the DL -
Mar. 10 No Class - Spring Break -
Mar. 13 No Class - Spring Break -
Mar. 17 More Memory; Lab 6: A Simple Memory System
Mar. 20 Building Larger Memory; Memory Parity and Error Correction
Mar. 24 Review; Introduction to Data Paths and Control Topic Notes: Data Path and Control; P&H Ch. 4.1-4.4
Mar. 27 Exam 2 (Digital Logic and Circuits)
Mar. 31 Pipelines and a Pipelined Data Path Topic Notes: Pipelines; P&H Ch. 4.5-4.6
Apr. 3 Pipelines: Dealing with Hazards P&H Ch. 4.7-4.8
Apr. 7 Pipeline Hazards Wrapup; Lab 7: Single-Cycle MIPS Subset Simulation -
Apr. 10 Control Hazards and Exceptions; Memory Hierarchies and Caches Topic Notes: Exceptions; P&H Ch. 4.9-4.10; Topic Notes: Memory Hierarchy; P&H Ch. 5
Apr. 14 Memory Hierarchy: Caches; Lab 8: Pipelined MIPS Subset Simulation
Apr. 17 Virtual Memory; ISA Comparisons Topic Notes: ISA Comparisons; P&H Ch. 2.17
Apr. 21 x86 Details; Parallelism Topic Notes: Parallelism; P&H Ch. 4.10
Apr. 24 Parallelism P&H Ch. 5.8; Topic Notes: Parallel Programming Introduction
Apr. 28 Exam Review; Parallel Programming
May 4 Final Exam: 3-6 PM, DCC 324 -